1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures in SOI configuration, having highly doped junctions with reduced junction capacitance.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are, and will be, based on silicon devices due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure and, therefore, one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile. A defined degree of blurring may be advantageous for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode. In other areas of the drain and source regions, that is, in deeper lying portions, the diffusion may result in a reduction of the dopant concentration at the corresponding PN junction areas, thereby reducing the conductivity at the vicinity of theses areas.
Thus, on the one hand, a high anneal temperature may be desirable in view of a high degree of dopant activation, re-crystallization of implantation-induced lattice damage and a desired diffusion at shallow areas of the extension regions, while, on the other hand, the duration of the anneal process should be short in order to restrict the degree of dopant diffusion in the deeper drain and source regions, which may reduce the dopant gradient at the respective PN junctions and also reduce the overall conductivity due to reducing the average dopant concentration. Furthermore, very high temperatures during the anneal process may negatively affect the gate insulation layer, thereby reducing the reliability thereof. That is, high anneal temperatures may degrade the gate insulation layer and thus may influence the dielectric characteristics thereof, which may result in increased leakage currents, reduced breakdown voltage and the like. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts may represent a dominant part for determining the transistor performance.
Recently, advanced anneal techniques have been developed in which extremely high temperatures may be achieved at a surface portion of the substrate, thereby transferring sufficient energy to the atoms for activating the dopants and re-crystallizing lattice damage wherein, however, the duration of the treatment is short enough to substantially prevent a significant diffusion of the dopant species and other impurities contained in the carrier material. Respective advanced anneal techniques are typically performed on the basis of radiation sources that are configured to provide light of appropriate wavelength that may be efficiently absorbed in upper portions of the substrate and any components formed thereon, wherein the effective duration of the irradiation may be controlled to a desired small time interval, such as a few milliseconds and significantly less. For instance, respective flash lamp exposure sources are available which provide light of a defined wavelength range resulting in a surface-near heating of material, thereby providing the conditions for short range motions of the respective atoms in the materials provided near the surface of the carrier material. In other cases, laser radiation may be used, for instance, in the form of short laser pulses or a continuous beam that may be scanned across the substrate surface on the basis of an appropriate scan regime in order to obtain the desired short term heating at each point on the substrate. Thus, contrary to traditional rapid thermal anneal (RTA) processes, in which frequently the entire carrier material may be heated to a desired temperature, the radiation-based advanced anneal techniques cause non-equilibrium conditions wherein a high amount of energy is supplied within extremely short time intervals, thereby providing the required extremely high temperatures at a very thin surface layer, while the remaining material of the substrate may remain substantially unaffected by the energy deposition during the anneal process. Thus, in advanced manufacturing regimes, traditional RTA processes may frequently be replaced by advanced radiation-based anneal processes in order to obtain a high degree of dopant activation and re-crystallization in drain and source regions while not unduly contributing to dopant diffusion, which may be advantageous in terms of a steep dopant gradient at the respective PN junctions. However, adjusting the effective channel length on the basis of a well-controlled diffusion of the dopants may be difficult to be integrated in the conventional process flow unless significant efforts may be made, thereby resulting in additional process complexity. On the other hand, the definition of the effective channel length on the basis of conventional well-established anneal techniques may require an increased spacer width and thus increased lateral dimensions of the transistor, when an efficient process flow is to be maintained.
A further issue related to the lateral and vertical dopant profile of the drain and source regions and thus of the PN junctions may be presented by the overall capacitance of the PN junctions, which is roughly related to the effective interface formed by the PN junctions with respect to the remaining active region of the semiconductor device. In order to further enhance the performance of SOI transistors, the parasitic capacitance of the PN junctions may be significantly reduced by designing the vertical dopant profile in such a manner that a high dopant concentration is obtained that extends down to the buried insulating layer. In this way, only the laterally oriented interface, i.e., the PN junction of the drain and source regions, contribute to the overall junction capacitance, while additionally the high dopant concentration extending down to the buried insulating layer provides the desired PN junction characteristics and also a reduced overall series resistance in the drain and source regions. However, providing deep drain and source regions with high dopant concentrations down to the buried insulating layer may require sophisticated implantation techniques, thereby contributing to the overall process complexity. In other cases, a moderately high dopant concentration at the buried insulating layer may be accomplished by adjusting the process parameters of the respective anneal processes in such a way that the diffusion of the dopants during the anneal process may result in the desired vertical dopant profile. The respective anneal parameters may, however, not be compatible with the requirement of a reduced transistor length, since also a lateral diffusion, for instance in the extension regions, may take place and result in a modified channel length which may therefore require increased spacer widths to accommodate the increased diffusion activity during a respective anneal process. Thus, high temperature anneal processes with extended process times for inducing high diffusion activity and thus generating a high thermal budget may be a less attractive approach in view of increasing the packing density of sophisticated semiconductor devices.
Moreover, techniques have been recently developed in which the transistor performance, for instance, the performance of P-channel transistors, may be significantly enhanced by providing a strained semiconductor material, such as a silicon/germanium compound, which may be formed in drain and source regions of silicon-based active transistor areas. The strained silicon/germanium compound, which may also be referred to as a silicon/germanium alloy, may be provided in a strained state due to a mismatch of the lattice spacing of natural silicon and natural silicon/germanium alloy. That is, the silicon/germanium material may be formed on the basis of the silicon lattice spacing, thereby resulting in a strained silicon/germanium crystal lattice, which may then interact with the neighboring semiconductor material to exert a stress and thus cause a certain strain. When providing the strained silicon/germanium alloy in the drain and source regions, the respective stress created by the strained material may act on the channel region of the transistor, thereby creating a respective compressive strain therein, which may enhance the charge carrier mobility therein. In highly scaled transistor devices based on the SOI architecture, significant benefits with respect to performance may be achieved by providing a highly strained semiconductor alloy in the vicinity of the channel region that extends along a significant portion in the depth direction in the semiconductor layer. Consequently, an efficient strain-inducing mechanism in SOI devices, in combination with a reduced parasitic junction capacitance, may result in an overall performance gain, while additionally a highly reduced thermal budget of the respective anneal processes may be desirable to provide the potential for reducing the lateral dimensions of the transistor devices, as explained above. Hence, in view of the situation described above, advanced techniques may be desirable for improving the transistor characteristics while not unduly contributing to process complexity and/or compromising the scalability of the respective process technique.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.